1. Technical Field
This disclosure is generally related to devices that perform floating point addition/subtraction operations. More specifically, this disclosure is related to devices that provide high-speed floating point half-adder capability.
2. Related Art
Modern computers generally include one or more floating point units used to perform operations on floating point values. Floating point values address the problem of limited dynamic range of integer and fixed point numeric representations. Often, the floating point values are represented and manipulated as described by IEEE standard 754 (and related standards). One skilled in the art will understand that generally a floating point value contains an exponent field, a sign field, and a mantissa field. The value in the exponent field ranges from positive to negative but can be biased (so that the exponent can be represented as an unsigned number). The mantissa field generally contains a normalized value (in some implementations, the normalized value may include an implicit bit that is always considered to be of value one for normalized floating point values). For subnormal floating point values (those having an exponent smaller than the smallest negative exponent in the range), the implicit bit is zero.
Floating point addition is an extremely common operation in numerically intensive applications (floating point subtraction is generally accomplished by complementing one of the operands and performing addition with carry). The IEEE 754 standard requires that the result of an operation should be the same as if the result were computed with extra precision, and then rounded (to a predetermined number of digits) using the floating point unit's current rounding mode (that can be represented by a rounding mode signal). IEEE standard 754 specifies four rounding modes: round to nearest, round to zero, round to +∞, and round to −∞. The default mode, round to nearest, chooses the even number in the event of a tie.
For this document, variable designations such as “A” implies a floating point value. Furthermore, designations such as—‘A’ mantissa—and—‘B’ exponent—represent the mantissa of “A” and the exponent of “B”. Also, —‘A’ operand—is the instruction operand that specifies “A”. One skilled in the art would understand that in some floating point adder implementations, the operands' values can be ordered such that the larger operand value (as determined from the ‘A’ and ‘B’ exponents) is the ‘B’ value. Where relevant, “A” is the smaller value and “B” is the larger value (when the ‘A’ and ‘B’ exponents are the same, the ‘A’ mantissa could be larger than the ‘B’ mantissa). In addition, the use of the term “signal” can represent one or more signals and/or a bus. For example, a signal may include multiple bits of a mantissa, a group of related signals that represent the result of a datapath, etc. If needed, any such ordering of “A” and “B” can be performed by the floating point unit or by a programmer or compiler.
A floating point unit generally includes multiple modules that perform the implemented floating point operations. One of these modules can be a floating point adder. The floating point adder can support a number of addition operations, for example, but without limitation, double/single precision floating point addition, floating point subtraction, floating point half operation, floating point comparison, etc.
Conceptually (and ignoring the subtle issues of maintaining precision, subnormal operands, and the details of rounding the result), the addition of “A” and “B” is performed by right-shifting the mantissa of the operand that has the smaller exponent such that the values of the operands have the same exponent (thus, the mantissas are aligned), then performing the addition operation, followed by rounding and normalizing the result of the addition. When a floating point value “A” is represented in accordance with IEEE standard 754, “A” can be divided by two by decrementing the ‘A’ exponent or by right-shifting the ‘A’ mantissa by one bit. One skilled in the art will understand that the right-shift approach is not compliant with IEEE 754 and can cause a loss of precision (this loss of precision can be somewhat mitigated by maintaining precision information such as the Guard, Round and Sticky bits).
Some floating point units support half-adder instructions. These half-adder instructions can include for example, a floating point half-add instruction, a half-subtract instruction and variants for both single and double precision floating point values. The half-adder instruction and half-subtract instructions are mathematically equivalent to
            (              B        +        A            )        2.0    ⁢          ⁢  and  ⁢          ⁢                    (                  B          -          A                )            2.0        .  That is, the result of the sum of two floating point values is divided by 2.0. One skilled in the art will understand that a half-subtract instruction operation is equivalent to a half-add instruction where, for example, “A” is a negative value. Such a one will also understand that, while
      (          B      -      A        )    2.0is mathematically equivalent to
            B      2.0        -          A      2.0        ,floating point precision constraints can result in different floating point values for these two calculations when processed by the floating point adder due to rounding.
One skilled in the art will understand the meaning of the terms “effective subtraction” and “effective addition” and will understand that, for example, operations such as B−A (where both “A” and “B” have positive values) and B+A (where “B” has a positive value and “A” has a negative value) are effective subtractions.
Conceptually, the half-adder instructions can be implemented in compliance with IEEE 754 by right-shifting the mantissa of the result of a standard addition operation by one bit position prior to the normalization step. A generally more accurate operation is that each of the operand's exponents can be decremented. Another approach is to right-shift the operands' mantissas by one prior to the add operation. While these approaches can work when the normalized operands are large (for example, when the difference in the operands' exponents is greater than two), they may not be in compliance with IEEE 754 when applied to subnormal floating point values, when performing a summation on two values that have the same exponent, or under other conditions.
FIG. 1 illustrates a prior art floating point half-adder architecture 100 that implements floating point add and half-adder instructions. These instructions operate on a pair of floating point values 101. The operands' signs, exponents, and mantissas are distinguished by a format operands logic 104 that accommodates whether the operands are single or double precision. The format operands logic 104 presents the formatted information to a determine half-adder conditions logic 105 that determines half-adder conditions such as whether the executing instruction is a half-adder instruction and the conditions and modes required to execute the half-adder instruction (as is subsequently described with respect to TABLE 1). These conditions, floating point unit rounding modes, operand exponents and operand mantissas (of the pair of floating point values 101) can contribute to a half-adder operation signal 107. The half-adder operation signal 107 can be presented to an exponent datapath logic 113 (EXP datapath), a large exponent difference datapath logic 115 (LED mantissa datapath), and a small exponent difference datapath logic 117 (SED mantissa datapath). The signals from each of these datapaths can be presented to a construct result logic 119. The large exponent difference datapath logic 115 and the small exponent difference datapath logic 117 each present a result mantissa to the construct result logic 119. An LED/SED select signal 121, that can be generated by the exponent datapath logic 113, can be presented to the construct result logic 119 and can be used to select which result mantissa is to be used when constructing (formatting) a floating point result value such as a floating point result 122.
The prior art floating point half-adder architecture 100 requires that the cycle time be lengthened and/or that an additional cycle be added to the floating point adder to accommodate the determine half-adder conditions logic 105. Thus, the addition of the half-adder instruction capability increases the computation time of the floating point adder and thus decreases its performance.
The summation mantissa from the large exponent difference datapath logic 115 can always be selected when the operation is an effective addition. The summation mantissa from the large exponent difference datapath logic 115 can also be selected if the operation is an effective subtraction where the operands' exponents are sufficiently different so as not to satisfy the conditions for the small exponent difference datapath logic 117. In many implementations, the summation mantissa of the small exponent difference datapath logic 117 can be selected when the operation is an effective subtraction and when the exponent difference between ‘A’ exponent and ‘B’ exponent is sufficiently small (for example, when the operands' exponents differ by zero or one).
The exponent datapath logic 113 can determine the mantissa shift needed to align the operands' mantissas. The exponent datapath logic 113 can also generate the LED/SED select signal 121 used to select which of the LED/SED datapath results will be used by the construct result logic 119.
In typical floating point adder implementations, the larger and smaller operand values are determined by comparing the operands' exponents. Generally, these implementations swap the operands' mantissas such that the ‘B’ mantissa is from the larger of the operands' values and the ‘A’ mantissa is from the smaller (as determined from the ‘Opr1’ and ‘Opr2’ exponents). The mantissas of the pair of floating point values 101 are aligned to the same order of magnitude (generally by right-shifting the mantissa of the operand having the smaller exponent by the difference between the operands' exponents—an alignment count) while maintaining rounding information for the shifted mantissa such as the Guard, Round and Sticky bits and the like.
The sign bits of the pair of floating point values 101, and subfield values of the instruction opcode can determine whether the floating point adder is to perform an effective addition or an effective subtraction. The appropriate operand's mantissa is complemented accordingly.
The aligned mantissas are added, rounded, and normalized in the LED and SED datapaths to compute the respective LED and SED summation mantissas. One of the summation mantissas computed by the large exponent difference datapath logic 115 and the small exponent difference datapath logic 117 is selected by the construct result logic 119 responsive to the LED/SED select signal 121.
FIG. 2 illustrates a prior art floating point adder process 200 that includes a format operands step 201 that determines the operands' signs, exponents, and mantissas responsive to whether the operands are single or double precision. Next, a determine operand conditions step 209 determines the conditions for the floating point adder instruction. These conditions include whether the instruction is a half-adder instruction and other conditions that are subsequently described with respect to TABLE 1. If the instruction is a half-adder instruction and depending on the conditions, an adjust operand decision step 211 determines the adjustment to the instruction's operands and will invoke either a right-shift mantissas step 215 to right-shift the mantissas of the operands by one, or will invoke a decrement exponents step 213 to decrement the exponents of the operands. The adjusted operands are then presented to a compute step 217 to perform the computation and normalize the result.
One skilled in the art will understand that FIG. 2 is illustrative, that the right-shift mantissas step 215 and the decrement exponents step 213 are only invoked if the instruction is a half-adder instruction and that some portions of the determine operand conditions step 209, the right-shift mantissas step 215 and/or the decrement exponents step 213 can be implemented within the compute step 217.
TABLE 1 lists the conditions that can be determined by the determine operand conditions step 209 and the corresponding operand adjustments used to support the half-adder instruction (one skilled in the art will understand the conditions for a half-negate-add instruction).
TABLE 1EffectiveOperandExponent ConditionHalf InstAdjustmentBoth operands' exponents greater thanhalf-add ordecrementtwo.half-subexponentsBoth operands' exponents equal to two.half-adddecrementexponentsOne operand's exponent equal to two,half-subdecrementand the other operand's exponent is notexponentsequal to one.Both operands' exponents less than two.half-add orright-shifthalf-submantissa by oneOne operand's exponent equal to two;half-subright-shiftother operand's exponent equal to one.mantissa by one
All prior implementations of the half-adder instructions known to the inventor include determining the half-adder conditions of TABLE 1. Once the exponent conditions are determined, the exponent datapath logic 113, the large exponent difference datapath logic 115, and the small exponent difference datapath logic 117 can be conditioned to perform additional operations to adjust the operands' values and compute the result of the half-adder instruction. The time to detect these conditions and to perform the operand adjustments adds to the computation time of existing floating point adders that incorporate half-adder capability. Thus, the performance of the floating point unit is reduced. What is needed is a floating point adder that implements half-adder instructions without determining the operand conditions prior to the start of the computation and that does not compromise the speed of execution of the floating point adder.